Ny FPGA-producent er klar til at gå i masseproduktion

Det er en næsten umulig opgave for et 'start-up' firma at etablere sig på FPGA-markedet. Men det ser ud til, at Achronix er kommet ud på den anden side, og firmaets Speedster22i familie er nu gået i produktion hos foundry-partneren Intel (in english).

The Speedster22i FPGA family is built on Intel’s 22nm Tri-Gate process technology and consists of three device members, two of which have entered production – the HD680 with 660 thousand effective look-up-tables (LUTs) and the HD1000 with 1 million effective LUTs.

Speedster22i FPGAs combine the most advanced production process technology node with the greatest amount of hardened interface IP currently available. The HD1000 has two 100 Gigabit Ethernet controllers, two 120 gigabit Interlaken controllers, two PCIe Gen3 x8 controllers and six 1866 Mbps DDR3 controllers – equivalent to 350,000 LUTs of logic that is eliminated from being implemented in the programmable fabric.

In addition to freeing up the programmable fabric, the hardened IP also speeds up development time because the IP meets timing and does not need to be placed and routed. The HD1000 also has 86 Mbit of on-chip RAM, 64 high performance SerDes lanes and almost a thousand programmable I/O.

- Developing high-end FPGAs with up to six billion transistors is complex and challenging. Achronix FPGAs with hard IP targeted for high performance wireline applications that are now in production offer a lower power and lower priced solution than the alternative general purpose FPGAs from other vendors,  says Steve Mensor, Vice President Marketing, Achronix. 

Advanced toolsuite

The Speedster22i family is supported by the Achronix CAD Environment (ACE) tool suite, which includes Synplify Pro for Achronix from Synopsys. Achronix also has development boards and a range of reference designs that accelerate development times and help customers reduce their time-to-market challenges.

Achronix has just realesed its latest tool suite, the Achronix CAD Environment (ACE) version 5.4, which now contains support for incremental compilation.

Incremental compilation dramatically increases productivity by allowing FPGA designers to compile portions of their design that have changed while leaving the remainder of their design intact. Incremental changes to a design can be passed through the entire tool flow efficiently, providing up to 58% speed-up compared to a non-incremental flow.

Compilation times are a critical consideration for FPGA designers. During both the design and prototype phases of an FPGA development, designers iterate their designs and verify functionality through simulation and system testing. The reduction of compilation times eliminates the bottleneck in this process and dramatically reduces the total development cycle time. In addition to compile time improvements, ACE 5.4 has achieved an average Fmax improvement of 30% compared to the initial release of ACE that supported Speedster22i FPGAs.

- Achronix changed the FPGA market when it introduced the Speedster22i FPGAs with hardened IP for high performance communication applications, says Steve Mensor.

- The hard IP not only reduces the power and cost of implementing high performance FPGAs for communication designs, but it dramatically reduces the development time, Mensor continues.
- The new incremental compilation support in ACE further reduces development times which allows customers to get their designs to market significantly faster. 

ACE 5.4 also adds a new, highly-configurable SerDes tuning GUI. This enables advanced, real-time SerDes link tuning and optimisation for the high-speed SerDes found on the Speedster22i family. With the SerDes link tuning GUI, designers can get their SerDes up and running in hours, further reducing their FPGA development time.